1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing an ion-implanted impurity layer with respect to a pattern of a polycrystalline silicon layer in a self-alignment manner.
2. Description of the Related Art
Self-alignment formation of impurity layers with respect to a pattern of a polycrystalline silicon layer is used for, for example, forming impurity layers of source/drain regions of transistors in manufacturing of conventional MOS transistors, which includes the following steps.
First, as illustrated in FIG. 2A, for example, an element isolation insulating film 12 and a gate insulating film 13 are formed on a silicon substrate 11. Subsequently, a polycrystalline silicon layer 14 is formed on the entire surface of the silicon substrate 11, and photoresist is then applied thereon. The resultant is exposed with a photomask corresponding to patterning of the polycrystalline silicon layer 14, to thereby form a first photoresist layer 15.
Next, as illustrated in FIG. 2B, the polycrystalline silicon layer 14 is removed by etching with the first photoresist layer 15 being a mask material, to thereby form gate electrodes 14-1 and 14-2 and a resistor 14-3 of the polycrystalline silicon layer 14, and wiring is formed. The first photoresist layer 15 is thereafter removed.
Next, as illustrated in FIG. 2C, a second photoresist layer 16 is patterned so that a source and a drain of a MOS transistor including a desired electrode, for example, the gate electrode 14-1 may be formed in desired regions. Source/drain impurity layers 17 are then selectively formed by ion implantation.
At this time, the opening portion of the second photoresist layer 16, through which ion implantation of impurities is performed, is formed not only above the desired source/drain regions of the MOS transistor, but also above the gate electrode 14-1. Thus, the gate electrode 14-1 functions as a mask for ion implantation, thereby enabling the source/drain impurity layers 17 to be formed to the gate electrode 14-1 in a self-alignment manner.
Manufacturing MOS transistors through those steps has the following advantages.
(1) It is not necessary to take misalignment between source/drain impurity layers and gate electrodes in photoresist pattern processing into consideration, and hence transistors can be miniaturized.
(2) It is not necessary to form a photoresist pattern for source/drain impurity layers needlessly finely, and hence at least the source/drain impurity layers can be formed more easily.
As described above, such a MOS transistor is formed that includes the source/drain impurity layers formed to the gate electrode pattern of the polycrystalline silicon layer in a self-alignment manner.
In addition, as illustrated in FIG. 2D, as needed, the above-mentioned step of FIG. 2C is repeatedly performed on desired regions in a MOS transistor including, for example, the gate electrode 14-2 as its electrode, to thereby form source/drain impurity layers 18 so that a plurality of kinds of MOS transistors can be formed.
MOS transistors including source/drain impurity layers formed in a self-alignment manner and methods of manufacturing the MOS transistor are well known. For example, in Seigo Kishino, “Basic VLSI material and process”, Ohmsha, Ltd., Dec. 25, 1987, pp. 11-12, there is disclosed a method of forming a source/drain impurity layer of a MOS transistor through the above-mentioned steps.
However, the following problems are found in the method of manufacturing a MOS transistor disclosed in Seigo Kishino, “Basic VLSI material and process”, Ohmsha, Ltd., Dec. 25, 1987, pp. 11-12.
A polycrystalline silicon layer, which is generally used as gate electrodes of transistors, is formed of an aggregate of single crystal grains. Thus, due to a channeling phenomenon in which implanted impurities pass through gaps between grains during ion implantation of source/drain impurities, impurities penetrate gate electrodes formed of a polycrystalline silicon layer, with the result that the impurities are also implanted into channel regions of transistors, which are formed in a silicon substrate and located below the gate electrodes.
This is a cause of greatly varying impurity concentrations of the channel regions, each of which is one important factor for determining a threshold of the transistor, and thus hinders stable transistor performance.